The SOI strained silicon schottky source/drain MOSFET with high-k gate dielectric is a potential device realizing small size MOSFET, which combines the advantages of strained silicon engineering, high-k gate dielectric, SOI structure and schottky source/drain. A model for the structure is proposed by solving two dimensional Possion’s equation, which takes into account for the impact on the source/drain schottky barrier height for electron of image force barrier and size quantization effect, then the drain induced barrier lower model is investigated based on the threshold voltage model. The experiment data of drain induced barrier lower extracted from literature is compared with the model, which verifies its correctness, and discuss the variety relationship between drain induced barrier lower and several parameters. The result shows that drain induced barrier lower increases with strained silicon thickness, channel doping and germanium fraction increasing, decreases with channel length, gate dielectric constant, intrinsic schottky barrier height for electron and drain source voltage increasing. The device can suppress drain induced barrier lower effect greatly through adjusting the model parameters properly, which can provide some reference for the design of SOI strained silicon schottky source/drain MOSFET with high-k gate dielectric device and circuit.
