Aiming at the problem that the restrictive bandwidth of the charge pump phase locked loop is restrictive, the self-biased charge pump phase locked loop with adaptive bandwidth whose bandwidth was modified dynamically according to the loop state was proposed. The maximal available bandwidth was proportional to the reference frequency and the restrain of the minimal reference frequency on the loop bandwidth was eliminated. The bandwidth was immune to the variation of the process, voltage and temperature. The loop bandwidth was modified according to the state of the loop, the noise of the output was reduced and the locking speed was improved. The standard of 0.18μm 1.8 V 1P6M CMOS logic process with N trap was used and the layout was 0.048 mm2. Experiment showed that the relative peak-peak jitter was less than 1.6 ％ when the reference frequency was from 2.8 MHz to 26.6 MHz. The power was less than 20 mW when the variations of process, voltage and temperature were less than 2.1 ％.
