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论文摘要

MPSoC核协调可靠性和性能的形式化验证

Formal Verification for Reliability and Performance on Core Coordination of MPSoC

作者:张晖(中国科学院成都计算机应用研究所);吴尽昭(广西民族大学 广西混杂计算与集成电路设计分析重点实验室);谢盈(中国科学院成都计算机应用研究所);曹俊月(中国科学院成都计算机应用研究所)

Author:zhanghui(Chengdu Institute of Computer Application, Chinese Academy of Sciences);wujinzhao(Guangxi Key Laboratory of Hybrid Computational and IC Design Analysis, Guangxi Uni-versity for Nationalities);xieying(Chengdu Institute of Computer Application, Chinese Academy of Sciences);caojunyue(Chengdu Institute of Computer Application, Chinese Academy of Sciences)

收稿日期:2015-12-14          年卷(期)页码:2016,48(3):107-114

期刊名称:工程科学与技术

Journal Name:Advanced Engineering Sciences

关键字:片上多核处理器; 核协调;混杂变迁系统; 混杂马尔科夫决策过程; 随机时序逻辑; PRISM模型检测器; 数据脱敏

Key words:multiprocessor system-on-chip; core coordination; hybrid labelled transition system; hybrid markov decision process; probabilistic computation tree logic; PRISM; data desensitization

基金项目:国家自然科学基金项目(11371003,11461006);广西科技基金项目(10169-1);广西自然科学基金(2012GXNSFGA060003);广西教育厅科研项目(201012MS274)

中文摘要

为了在早期发现片上多核处理器(MPSoC)设计缺陷,本文提出了一种对核协调进行结构建模和性质刻画的形式化方法。在标记变迁系统中引入多项式函数替代动作表达核协调过程中对数据的改变,加入物理元器件发生故障的概率属性,形成用以描述核协调可靠性和性能的混杂马尔科夫决策过程模型。采用随机时序逻辑刻画系统性质,通过模型检测工具验证分析,以银行数据脱敏MPSoC为例,分析系统可靠性和时间延迟与能耗等性能指标。这些验证结果对于早期MPSoC设计人员具有较强的指导作用。

英文摘要

In order to discover MPSoC's design defect earlier, a formal method for depicting core coordination was proposed, including structural model and logical characterization. The main idea was to adopt polynomial functions to replace actions on labelled transition system to describe data changes among different states. Combining with the malfunctioning probability of physical components, a hybrid Markov decision process model was formulated to describe the reliability and performance of the core coordination. Then system properties was depicted by the probabilistic computation tree logic and verified by model checker. Finally, an experiment using data desensitization MPSoC in banks was carried out and a result including the system reliability and time latency as well as power consumption was analyzed. The study is valuable for early MPSoC designers.

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